Voltage regulators, such as DC to DC converters, are used to provide stable voltage sources for electronic systems. Efficient DC to DC converters are particularly needed for low power devices. One type of DC-to-DC converters is a switching voltage regulator. A switching voltage regulator generates an output voltage by alternately coupling and decoupling an input DC voltage source with a load. The coupling and decoupling action can be performed by a switch, while a low pass filter comprising a capacitor and an inductor can be used to filter the output of the switch to provide a DC output voltage.
FIG. 1 shows an example implementation of a “buck” type switching regulator, which can perform a DC-DC down conversion. Referring to FIG. 1, circuit 100 includes a voltage source 103, a switching regulator 102 and a load 113. Switching regulator 102 is coupled to the voltage source 103 through an input terminal 114. Switching regulator 102 is also coupled to the load 113, which can be another electronic circuit that draws current, via an output terminal 112. Switching regulator 102 includes a switching circuit 116, which serves as a power switch for alternately coupling and decoupling input terminal 114 to an intermediate terminal 109. Switching circuit 116 includes a first transistor 107 and a second transistor 108. Typically both transistors 107 and 108 can be implemented as metal oxide semiconductor field effect transistor (MOSFETs). Transistor 107 has a drain connected to input terminal 114, a source connected to an intermediate terminal 109, and a gate connected to a control line 105. Transistor 108 has a drain connected to intermediate terminal 109, a source connected to a low voltage potential 115 (e.g. a ground), and a gate connected to a control line 106.
Switching regulator 102 includes a controller 104 to control the operation of switching circuit 116 via control lines 105 and 106. Switching regulator 102 also has an output filter 117, which includes an inductor 110 connected between intermediate terminal 109 and output terminal 112, and a capacitor 111 connected in parallel with load 113. Controller 104 causes switching circuit 116 to alternate between a first conduction period, where first transistor 107 is enabled and second transistor 108 is disabled to bring intermediate terminal 109 to a voltage substantially equal to the input voltage, and a second conduction period, where first transistor 107 is disabled and second transistor 108 is enabled to bring intermediate terminal 109 to a voltage substantially equal to that of low voltage potential 115. This results in a rectangular waveform, which toggles substantially between input voltage and a voltage equal to voltage potential 115, at intermediate terminal 109. Intermediate terminal 109 is coupled to output terminal 112 via output filter 117. Output filter 117 converts the rectangular waveform at intermediate terminal 109 to a substantially DC voltage at output terminal 112. The magnitude of the output DC voltage at terminal 112 depends on the duty cycle of the rectangular waveform at intermediate terminal 109.
With widespread use of BCD (Bipolar-CMOS-DMOS) technology, it is common to integrate controller 104, switching circuit 116, as well as high precision feedback circuit (not shown in FIG. 1) on the same chip. In most monolithically integrated switching regulators with the input operating range of 10 to 200 V, lateral double diffused MOSFET (LDMOS) power devices are used as switch elements.
FIG. 2 illustrates a perspective view of a conventional LDMOS device. As shown in FIG. 2, LDMOS device 200 includes a substrate 202, which is doped with either a P-type or N-type material. On top of substrate 202, device 200 has a body region 203, which is doped with the same type of material as substrate 202. Device 200 also includes a drift region 208, which is doped with an opposite type of material to body region 203 (e.g., doped with N-type if body region 203 is P-type). An isolation region 205, which can be an oxide filled trench such as a shallow trench isolation (STI) region, is formed within drift region 208. Device 200 also includes a source region 206 and a drain region 209, each of which is doped with an opposite type of material to body region 203. Drain is accessed through a drain terminal 215 that is coupled to drain region 209. Device 200 also includes a body contact region 204 abutting source region 206. The abutting regions 204 and 206 are doped with opposite types of materials. Regions 204 and 206 are tied together with a shared contact that is accessed through a body/source terminal 214. Device 200 also includes a gate 201, which includes a gate electrode layer 207, for example, made of polysilicon, a gate terminal 216, and an insulation layer 220, such as silicon dioxide, below gate electrode layer 207. Insulation layer 220 overlaps with region 211 to form the channel, and overlaps with regions 202 and 212 to form an accumulation, transition or neck region. In some embodiments, insulation layer 220 extends from the edge of source region 206 to overlap isolation region 205. The overlapping region is typically called the field plate region (denoted 213 in FIG. 2).
With the configuration shown in FIG. 2, applying a bias voltage of the right polarity to the gate terminal 216 can induce a charge-carrying channel to be formed, in a process known as inversion, at the region 211 under the gate oxide where gate 201 overlaps body region 203. Terminal 214 can act as the source of the LDMOS device. Flow of current from drain to source can be initiated by the application of a bias voltage to drain terminal 215. As the device is turned on, channel inversion charges from the channel 211 flows through transition region 212 and drift region 208 under isolation region 205, to drain region 209, and then out of drain terminal 215.
In the LDMOS device 200 in FIG. 2, a high off-state drain-source voltage can be tolerated by the drift region 208 which is separated from the channel by the accumulation or the transition region. Transition region helps optimize the device on-resistance and breakdown. However, since the transition region is over-laid by the gate oxide, which is typically thin, the transition region introduces considerable Miller capacitance and constitutes a significant portion of the overall gate charge leading to large switching losses in converter circuits. There are prior attempts to mitigate the Miller capacitance. For example, U.S. Patent Application Publication No. 2011/0115018 to McGregor (hereinafter “McGregor”), filed on Nov. 13, 2009, entitled “MOS Power Transistor,” introduces a split-gate structure. Although the technique in McGregor reduces the gate area over the drift region and the transition region, the remaining field plate (formed by splitting the gate) in McGregor requires extra wire connection to the source. This complicates internal device wiring and introduces extra output capacitance by coupling the drain to the field plate and the source.
Hence, there is a need for a technique to reduce the gate capacitance of power MOSFETs, especially for LDMOS devices, which neither requires extra wiring without addition of extra device output capacitance as it attempts to reduce the input capacitance.